1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device, more particularly to a method for manufacturing a semiconductor device with removing a hardened layer on a resist surface with reducing damages on a base layer.
2. Description of the Related Art
As semiconductor devices become highly integrated to have higher performance, dry etching technologies for fine processing on various materials are also required to be more improved. The semiconductor manufacturing industry is required to produce various types but less lots such as ASIC (Application Specified IC). Under such the situation, single wafer dry etchers have been the mainstream instead of batch loades dry etchers. The single wafer dry etcher, however, is required to improve etching rate per wafer, in order to realize the same output as the batch loades dry etcher. For the etching rate improvement, the single wafer dry ether performs etching under gained incident energy of reactive species.
As the incident energy of the reactive species is highly gained, a resist surface is exposed to highly energized ions or electrons. As a result, the resist surface is hardened, and a hardened surface layer may appears. Such the resist having the hardened surface layer may be ashed incompletely at a later step. Or, the hardened surface layer may be scattered to form particles. Those will deteriorate yielding of a semiconductor device.
Moreover, since highly energized ions are implanted into a base layer, the base layer is damaged, thus, a damaged layer may appear on the base layer surface. The damaged layer will also deteriorate the device characteristics of the semiconductor device.
The problems in the etching with highly energized active species will now be described with reference to FIGS. 6A to 6C. As shown in FIG. 6A, a semiconductor wafer to be processed has a base layer 601 in which plugs 602 (base) are formed, an interlayer film formed on the base layer, and a resist 604 formed on the interlayer film 603 as an etching mask.
The surface of the resist 604 is exposed to highly energized ions or electrons through this process. As a result, the surface of the resist 604 is hardened, thus a hardened resist surface layer 605 is formed as shown in FIG. 6B. When highly energized ions are implanted into the plug 602, the surface of the plug 602 is damaged by the ion implantation, thus a damaged layer 606 is formed as shown in FIG. 6B.
Thus formed hardened resist surface layer 605 and damaged layer 606 are remained after ashing, as shown in FIG. 6C. Such the residues should be removed because they will deteriorate performance of the semiconductor device.
The hardened resist surface layer 605 and the damaged layer 606 are removable at removing steps prepared for each. However, such the additional steps may cause throughput deterioration or cost increase. Unexamined Japanese Patent Application KOKAI Publication No. H6-177092 discloses a method for removing the hardened resist surface layer 605 or the damaged layer 606 without the throughput deterioration or cost increase caused by increased number of steps. The disclosed method utilizes a plasma generation gas including O2 (oxygen) for the removing.
In this method, an ECR (Electron Cyclotron Resonance) plasma etcher etches a silicon compound layer with using an etching gas including fluorocarbons, and introduces O2 after the etching to generate ECR plasma. A hardened resist surface layer and a damaged layer are removed by oxygen (O) radical which appears during plasma generation, or fluorine (F) radical which is generated by reaction of residual gas with O2. RF (Radio Frequency) bias are applied to the hardened resist surface layer and the damaged layer during the etching, and the RF bias is cut off after the etching, thus, the hardened resist surface layer and the damaged layer are removed. That is, the RF bias is cut off to lower the energy of the active species such as ions. As a result, the hardened resist surface layer and the damaged layer are removed without etching the silicon compound layer excessively.
This method is applicable to an ECR plasma etcher or the like which carries out ashing at every processing per substrate, however, it is not suitable for a parallel plate plasma etcher with upper electrodes made of silicon (Si).
FIG. 7 shows a parallel plate plasma etcher 701. The etcher 701 comprises an etching chamber 702 which houses a pair of parallel plate electrodes of an upper electrode 703 and a lower-electrode/wafer-holder 704. With an electrostatic attractive stage 705, a target wafer W is attracted to the lower-electrode/wafer-holder 704. High frequency electricity is supplied to the upper electrode 703 and the lower-electrode/wafer-holder 704 from high frequency power sources 706 (for the upper electrode) and 707 (for lower electrode) respectively. The power supply generates high density plasma P for the etching.
In a case where a silicon oxide (SiOx) film is etched by fluorocarbons in the above described parallel plate plasma etcher 701, the high density plasma helps dissociate the fluorocarbons, thus, generation of the mass of F radicals often occurs. The excessively generated F radicals decrease selective ratio of the SiOx film to Si compound other than the SiOx film, or to the resist. It is undesirable for fine etching. To reduce the excessively generated F radicals, the upper electrode 703 is made of Si, which has high reactivity for F radicals. That is, the excessively generated F radicals are trapped by Si of the upper electrode so that F radicals are reduced.
As aforementioned, the high frequency electricity is applied to the upper electrode 703. In a case where the upper electrode 703 is made of Si, active etching species collide with the upper electrode 703, thus the upper electrode 703 is sputtered. As a result, Si atoms often spring out from the upper electrode 703 toward the resist surface. The Si atoms deposited on the resist surface may form a hardened resist surface layer.
As well as the case of the ECR plasma etcher, the hardened resist surface layer formed by the Si atoms are removable by ECR plasma which is generated by introduced O2 following to cutting off the power supply to the upper electrode 703 and the lower-electrode/wafer-holder 704 after the SiOx film is etched. However, since the hardened resist surface layer is made of Si compound, it must be subjected to long time processing with O radical rich or F radical rich plasma, in order to remove the Si compound. Moreover, elongation of plasma exposing period causes isotropic etching on the SiOx film. As a result, the etching profile of the SiOx film is deteriorated, and the base layer is damaged during the etching.
Not only the case of the above described parallel plate etcher employing Si upper electrode, but also any cases are undesirably affected by extra steps for removing the hardened resist surface layer and the damaged layer after interlayer etching steps. That is, the extra steps causes throughput deterioration and increase of facility costs. Moreover, interlayer films or a base layer may be etched undesirably.
The present invention has been made in consideration of the above problems, it is an object of the present invention to provide a method and an apparatus for manufacturing a semiconductor device which remove a hardened resist surface layer without causing throughput deterioration, facility cost increase, and damages on a base layer.
To achieve the above object, a method of manufacturing a semiconductor device according to the present invention comprises the steps of:
preparing a process target on which pattern of a resist is formed;
firstly etching the target with masking the target by the pattern of the resist with using a first etching gas; and
secondarily etching the target with using a second etching gas instead of the first etching gas, and simultaneously removing a hardened layer formed on a surface of the resist during the first etching step.